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DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips

US patent 8,914,692, Issued on Dec 16, 2014

 

Testing for Small Delay Defects in Nanoscale CMOS Integrated Circuits

 

October 25, 2013 by CRC Press 
ISBN 9781439829417 

Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects (SDDs) in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations.

 

Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.

 

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