SANDEEP K GOEL

S.K. Goel, "2.5D-SICs: Do We Need To Test The Interposer, And If So, How?", Panelist at IEEE International Workshop on Testing 3D Stacked Integrated Circuits (3D-Test), CA, USA, 2014

 

S.K. Goel, “Where is 3D test going? Is it a new mainstream or a marginal trend?" Panelist at IEEE International Test Conference (ITC), CA, USA, 2013

 

S.K. Goel, "How are failure modes, defect types and test methods changing for 32 nm/28 nm and beyond?" Panelist at IEEE International Test Conference (ITC), CA, USA, 2012

 

S.K. Goel and B. Petrakis, "What does it take to build an end-to-end test flow for 3D-IC stacks?” Presentation at 20th Electronic Design Process Symposium (EDPS), CA, USA, 2012

 

S.K. Goel,"Industry Leaders Panel - How will testing change in the next 10 years?" Panelist at IEEE International Test Conference (ITC), CA, USA, 2011

 

S.K. Goel, "Test challenges and solutions for Wide-I/O DRAM stacking", Panelist at IEEE International Workshop on Testing 3D Stacked Integrated Circuits (3D-Test), CA, USA, 2011

 

N. Devta-Prasanna and S.K. Goel, "Test pattern generation methods for small delay defect testing", Presentation at Mentor Graphics's User2User Conference, CA, USA, 2009

 

S.K. Goel and M. Ward. "Value of DFM in volume diagnosis arena", Industrial practice session at IEEE VLSI Test Symposium (VTS), CA, USA, 2009

 

S.K. Goel, "Commercial tools for RTL design-for-test Exist but how good are they?" Panelist at IEEE European Test Symposium (ETS), Italy, 2008

 

S.K. Goel, G. Eide, and R. Thompson, "Physical-aware ATPG: What does it really mean?" Presentation at IEEE European Test Symposium  (ETS), Italy, 2008

 

S.K. Goel, "Multi-site test", Industrial practice session at IEEE VLSI Test Symposium, CA, USA, 2005

 

E.J. Marinissen and S.K. Goel, "SOC test infrastructure optimization under layout constraints", Presentation at IEEE VLSI Test Symposium (VTS), CA, USA, 2003