top of page

I grew up in a small city called 'Meerut' in Uttar Pradesh, India. In the history of India, this city has got a very significant place because of it's contribution to the 1857 freedom fight against British rulers. I spend almost 19 years of my life in Meerut. I received B.Tech degree in Electronics & Communication from Institute of Engineering & Technology (IET), Lucknow, M.Tech degree in VLSI Design Tools and Technology from Indian Institute of Technology (IIT), Delhi, and a Ph.D. degree in Electrical Engineering from the University of Twente, The Netherlands. Since 2010, I am a TSMC Academician/Senior Manager  with Taiwan Semiconductor Manufacturing Company (TSMC), San Jose, CA. Prior to TSMC, I was in various research positions with LSI Corporation CA, Magma Design Automation, CA, and Philips Research, The Netherlands.

 

I have co-authored two books, three book chapters, and published over 80 papers in journals and conference/workshop proceedings. I have delivered several invited talks and have been panelist at several conferences. I hold 21 U.S. and 5 European patents and have over 30 other patents pending. I was a recipient of the Most Significant Paper Award at the IEEE International Test Conference in 2010. I serve on various conference committees and IEEE Standardization groups including DATE, ETS, DAC, ITC, VLSI-DAT, 3DTest, and IEEEP1838. I was the General Chair of 3D Workshop at DATE 2012. I am a senior member of the IEEE. My current research interests include all topics in the domain of testing, stacking, diagnosis and failure analysis of 2D/3D chips in sub-nanometer (10nm and below) technologies. In my free time, I like listening to music, swimming or cooking/baking. I plan to have my own book series on traditional and modern cooking sometime in future....

 

bottom of page