Researcher, Inventor & Author
SANDEEP K GOEL
US Patents
DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips
US patent 8,914,692, Issued on Dec 16, 2014
DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips
US patent 8,873,320, Issued on Oct 28, 2014
Probe card partition scheme
US patent 8,836,363, Issued on Sept 16, 2014
Reducing design verification time while maximizing system functional coverage
US patent 8,826,202, Issued on Sept 2, 2014
System and method for testing stacked dies
US patent 8,751,994, Issued on Jun 10, 2014
Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designs
US patent 8,707,238, Issued on Apr 22, 2014
Multi-dimensional integrated circuit structures and methods of forming the same
US patent 8,686,570, Issued on Apr 1, 2014
System and device for reducing instantaneous voltage droop during a scan shift operation
US patent 8,627,160, Issued on Jan 7, 2014
Format conversion from value change dump (VCD) to universal verification methodology (UVM)
US patent 8,578,309, Issued on Nov 5, 2013
Method for detecting small delay defects
US patent 8,566,766, Issued on Oct 22, 2013
Circuit and method for diagnosing scan chain failures
US patent 8,566,657, Issued on Oct 22, 2013
System and method for testing stacked dies
US patent 8,561,001, Issued on Oct 15, 2013
Test prepared integrated circuit with an internal power supply domain
US patent 8,552,734, Issued on Oct 8, 2013
Testing of an integrated circuit that contains secret information
US patent 8,539,292, Issued on Sept 17, 2013
Method and an apparatus for evaluating small delay defect coverage of a test pattern set on an IC
US patent 8,515,695, Issued on Aug 20, 2013
Circuits and methods for testing through-silicon vias
US patent 8,436,639, Issued on May 17, 2013
Stacked die interconnect validation
US patent 8,402,404, Issued on Mar 19, 2013
Method for generating test patterns for small delay defects
US patent 8,352,818, Issued on Jan 8, 2013
Test circuit and method for testing of infant mortality related defects
US patent 8,140,923, Issued on Mar 20, 2012
Test circuit and method for hierarchical core
US patent 7,380,181, Issued on May 27, 2008
Testing of circuit with plural clock domains
US patent 7,076,709, Issued on Jul 11, 2006
EU Patents
Testing of an integrated circuit that contains secret information
EU patent 1,915,632
Testing of an integrated circuit that contains secret information
EU patent 1,917,535
Method for generating test patterns for small delay defects
EU patent 8,352,818
Test prepared integrated circuit with an internal power supply domain
EU patent 1,875,258
Test circuit and method for hierarchical core
EU patent 1,787,136
Testing of circuit with plural clock domains
EU patent 1,472,551