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Book Chapters
S.K. Goel and K. Chakrabarty, “Power-aware BIST and test data compression”, Book ‘Power-Aware Testing and Test Strategies for Low Power Devices’, ISBN 978-1-441909275, Springer, USA, 2009 

 

S.K. Goel and E.J. Marinissen, “On-chip test infrastructure design for optimal multi-site testing”, Book ‘System on Chip: Next Generation Electronics, ISBN 978-0863415524, IEE Press, UK, 2006

 

S.K. Goel and E.J. Marinissen, “Test resource management and scheduling for modular manufacturing test of SOCs”, Book ‘Algorithms in Ambient Intelligence’, Volume 2, ISBN 978-1-4020-1757-5, Kluwer Academic Publishers, The Netherlands, 2004

 

Journals

C.C. Chi, E.J. Marinissen, S.K. Goel, and C.W. Wu, “Low-cost post-bond testing of 3D-SICs containing a passive interposer base”, IEEE Transactions on Computer-Aided Design, 2014 
 
E.J. Marinissen, M. Konijnenburg, S. Deutsch, V. Chickermane, B. Keller, and S.K. Goel, “Automation design-for-test for 2.5D- and 3D SICs”, Chip Scale Review Magazine, Sep-Oct 2011, pp. 18-22, 2011
 
B. Noia, K. Chakrabarty, S.K. Goel, E.J. Marinissen, J. Verbree, “Test architecture optimization and test scheduling for TSV-based 3D stacked ICs”, IEEE Transactions on Computer-Aided Design of ICs and Systems, vol. 30, no. 11, November, 2011
 
S.K. Goel, E.J. Marinissen, A. Sehgal, and K. Chakrabarty, “Testing of SOCs with hierarchical cores: Common fallacies, test access optimization, and test scheduling”, IEEE Transactions on Computers, vol. 58, no. 3, pp. 409-423, March, 2009
 
S.K. Goel and E.J. Marinissen, “Will test compression run out of gas?” ITC 2008 panel summary, IEEE Design & Test of Computers, December, 2008
 
S.K. Goel, M. Meijer, and J.P. de Gyvez, “Efficient testing and diagnosis of faulty power switches in SOCs”, Proceedings IEE Computers & Digital Techniques, vol. 1, issue 8, pp. 230-236, May, 2007
 
E.J. Marinissen and S.K. Goel, “Zero defects: Mission impossible?” ITC 2006 panel summary, IEEE Design & Test of Computers, vol 24, no. 1, pp. 94-96, January, 2007
 
S.K. Goel and E.J. Marinissen, “Optimization of on-chip design-for-test infrastructure for maximal multi-site test throughput”, Special issue ‘Embedded Microelectronics Systems: Status and Trends’ of IET Proceedings Computer and Digital Techniques, vol. 152, no, 3, June, 2005
 
S.K. Goel and E.J. Marinissen, “SOC test architecture design for efficient utilization of test bandwidth”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 8, issue 4, pp. 399-429, Oct., 2005
 
S.K. Goel and E.J. Marinissen, “A test time reduction algorithm for test architecture design for core-based system chips”, Journals of Electronic Testing: Theory and Application, vol. 19, issue 4, pp. 425-435, Aug., 2003
 
S.K. Goel and B. Vermeulen, “Data invalidation analysis for scan-based debug on multiple-clock system Chips”, Journals of Electronic Testing: Theory and Application (JETTA), vol. 19, issue 4, pp. 407-416, Aug., 2003
 
S.K. Goel and B. Vermeulen, “Design-for-debug: Your safety net for catching design errors in digital chips”, IEEE Design & Test of Computers, vol. 2, May, 2002

 

Conferences

S.K. Goel, M.J. Wang, S. Adham, A. Mehta, and F. Lee, “Design-for-Diagnosis: your safety net in catching design errors in 3rd party dies in 3D/CoWoS ICs”, IEEE International Symposium on VLSI Design, Automation and Test, Taiwan, 2014

 

S.K. Goel, S. Adham, M.J. Wang, J.J. Chen, T.C. Huang, A. Mehta, F. Lee, V. Chickermane, B. Keller, T. Valind, S. Mukherjee, N. Sood, J. Cho, and H.H. Lee, “Test and debug strategy for TSMC CoWoSTM stacking process based heterogeneous 3D IC: A silicon case study”, IEEE International Test Conference (ITC), CA, USA, 2013

 

S. Deutsch, V. Chickermane, B. Keller, S. Mukherjee, N. Sood, S.K. Goel, A. Mehta, F. Lee, and E.J. Marinissen, “DFT architecture and ATPG for interconnect test of JEDEC Wide-IO memory-on-logic die stacks”, IEEE International Test Conference, CA, 2012

 

S.K. Goel, “Test challenges in designing complex 3D chips: What is on the horizon for the EDA Industry?” IEEE International Conference on Computer-Aided Design (ICCAD), CA, USA, 2012

 

E.J. Marinissen, G. Vandling, S.K. Goel, F. Hapke, J. Rivers, N. Mittermaier, and S. Bahl, “EDA solutions to new-defect detection in advanced process technologies”, Design Automation and Test in Europe (DATE), Dresden, Germany, 2012

 

E. Beyne, M. Konijnenburg, E.J. Marinissen, L. Jensen, S. Deutsch, V. Chickermane, B. Keller, S. Mukherjee, and S.K. Goel, “Automation of DFT for 3D stacked die”, 3-D Architectures for Semiconductor Integration and Packaging (3D-ASIP), CA, 2011

 

S. Deutsch, V. Chickermane, B. Keller, S. Mukherjee, M. Konijnenburg, E.J. Marinissen, and S.K. Goel, “3D-DFT automation: Testing of stacked integrated circuits that use through silicon vias”, NMI Network Event ‘Fit for manufacture: Using DFT to deliver on cost, quality and TTM’, UK, 2011

 

C.C. Chi, E.J. Marinissen, S.K. Goel, and C.W. Wu, “Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base”, IEEE Asian Test Symposium, India, 2011

 

S. Deutsch, V. Chickermane, B. Keller, M. Konijnenburg, E.J. Marinissen, and S.K. Goel, “Automation of 3D DFT insertion”, IEEE Asian Test Symposium (ATS), India, 2011

 

C.C. Chi, E.J. Marinissen, S.K. Goel, and C.W. Wu, “DFT architecture for 3D-SICs having multiple towers”, IEEE European Test Symposium (ETS), Norway, 2011

 

S.K. Goel, G. Vandling, C. Liu, W.P. Changchien, and N.H. Tseng, “How real are small delay defects: A silicon case study”, Lecture series, IEEE International Test Conference (ITC), CA, 2011

 

C.C. Chi, E.J. Marinissen, and S.K. Goel, “Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base”, IEEE International Test Conference (ITC), CA, 2011

 

S. Deutsch, V. Chickermane, B. Keller, M. Konijnenburg, E.J. Marinissen, and S.K. Goel, “Automation of 3D DFT insertion and interconnect test generation”, IEEE International Test Conference, CA, 2011

 

S.K. Goel, K. Chakrabarty, M. Yilmaz, K. Peng, and M. Tehranipoor,“Circuit topology-based test pattern generation for small delay defects”, IEEE Asian Test Symposium (ATS), China, 2010 
(selected in ‘ATS 20th anniversary compendium of selected papers’)

 

B. Noia, S.K. Goel, K. Chakrabarty, E.J. Marinissen, and J. Verbree,“ Test architecture optimization for TSV-Based 3D Stacked ICs”, IEEE European Test Symposium (ETS), Czech Republic, 2010

 

S.K. Goel, N. Devta-Prasanna, and M. Ward, “Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study”, IEEE International Test Conference, TX, 2009

 

N. Devta-Prasanna, S.K. Goel, A. Gunda, M. Ward, and P. Krishnamurthy, “Accurate measurement of small delay defect coverage of test patterns”, IEEE International Test Conference, TX,  2009

 

S.K. Goel, N. Devta Prasanna, and R. Turakhia, “Effective and efficient test pattern generation for small delay defects”, IEEE VLSI Test Symposium (VTS), CA, 2009

 

R. Turakhia, M. Ward, S.K. Goel and B. Benware, “Bridging DFM analysis and volume diagnosis for yield learning”, IEEE VLSI Test Symposium (VTS), CA, 2009

 

S.K. Goel and E.J. Marinissen, "Testing of 3D chips: Is there anything new under the sun?", IEEE International Test Conference (ITC), TX, 2009

 

S.K. Goel and E.J. Marinissen, “Will test compression run out of gas?”, IEEE International Test Conference (ITC), CA, 2008

 

S.K. Goel and E.J. Marinissen, “Zero Defects: Mission Impossible?”, IEEE International Test Conference (ITC), CA, 2006

 

H. Vranken, S.K. Goel, A. Glowatz, J. Schloeffel, and F. Hapke, “Fault detection and diagnosis with parity trees for space compaction of test responses”, Design Automation Conference (DAC), CA, 2006

 

S.K. Goel, M. Meijer, and J.P. de Gyvez, “Test and diagnosis of power switches in SOCs”, IEEE European Test Symposium (ETS), UK, 2006

 

A. Sehgal, S.K. Goel, E.J. Marinissen, and K. Chakrabarty, "Hierarchy-aware and area-efficient test infrastructure design for core-based system chips", Design Automation and Test in Europe (DATE), Germany,  2006

 

U. Ingelsson, S.K. Goel, E. Larsson, and E.J. Marinissen, "Test scheduling for modular SOCs in an abort-on-fail environment", IEEE European Test Symposium (ETS), Estonia, 2005

 

S.K. Goel and E.J. Marinissen, "On-chip test infrastructure design for optimal multi-site testing of system ships", Design Automation and Test in Europe (DATE), Germany, 2005

 

A. Sehgal, S.K. Goel, E.J. Marinissen, and K. Chakrabarty, "P1500-compliant test wrapper design for hierarchical cores", IEEE International Test Conference (ITC), NC, USA, 2004

 

S.K. Goel and E.J. Marinissen, "TR-Architect: DFT and test support for SOC designers", ProRISC Workshop on Circuits, Systems, and Signal Processing (ProRISC), Netherlands,  2004

 

B. Vermeulen, Z. Urfianto, and S.K. Goel, "Automatic generation of breakpoint hardware for silicon debug", Design Automation Conference (DAC), CA, USA, 2004

 

L. Krundel, S.K. Goel, E.J. Marinissen, M.L. Flottes, and B. Rouzeyre, "User-constrained test architecture design for modular SOC testing", IEEE European Test Symposium (ETS), France, 2004

 

S.K. Goel, "A novel wrapper cell design for efficient testing of hierarchical cores in system chips", IEEE European Test Symposium (ETS), France, 2004

 

S.K. Goel and E.J. Marinissen, "Reducing test cost: How much multi-site can you handle?", IEEE European Test Symposium (ETS), France, 2004

 

S.K. Goel, K. Chiu, E.J. Marinissen, T. Nguyen, and S. Oostdijk, "Test infrastructure design for the NexperiaTM home platform PNX8550 system chip", Design Automation and Test in Europe (DATE), France, 2004

 

S.K. Goel and E.J. Marinissen, "Control-aware test architecture design for modular SOC testing", IEEE European Test Symposium (formerly European Test Workshop), Netherlands, 2003

 

S.K. Goel and E.J. Marinissen, "Layout driven test architecture design of SOCs for test time and wire length minimization", Design Automation and Test in Europe (DATE), Germany, 2003

 

S.K. Goel and E.J. Marinissen, "Test resource management and scheduling for modular manufacturing test of SOCs", Philips’ Symposium on Intelligent Algorithms (SOIA), The Netherlands, 2002

 

S.K. Goel and B. Vermeulen, "Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips", IEEE International Test Conference (ITC), MD, USA, 2002

 

V. Iyenger, S.K. Goel, E.J. Marinissen, and K. Chakrabarty, "Test resource optimization for multi-site testing using ATE with memory depth constraints for SOCs", IEEE International Test Conference (ITC), US, 2002

 

B. Vermeulen, T. Waayers, and S.K. Goel, "Core-based scan architecture for silicon debug", IEEE International Test Conference (ITC), MD, USA, 2002

 

S.K. Goel and E.J. Marinissen, "A novel test time reduction algorithm for test architecture design for core-based system chips", IEEE European Test Symposium (ETS), Greece, 2002

 

S.K. Goel and B. Vermeulen, "Data invalidation analysis for scan-based debug on multiple-clock system chips", IEEE European Test Symposium (ETS), Greece, 2002

 

E.J. Marinissen and S.K. Goel, "Analysis of test bandwidth utilization in test bus and testrail architectures for SOCs", IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop (DDECS), Hungary, 2002

 

S.K. Goel and E.J. Marinissen, "Cluster-based test architecture design for system-on-chip", IEEE VLSI Test Symposium (VTS), CA, USA, 2002

 

E.J. Marinissen, S.K. Goel, and M. Lousberg, "Wrapper design for embedded core test", IEEE International Test Conference (ITC), NJ, USA, 2000 (Selected as one of the most significant papers in last 35 years of ITC)

Workshops

S. Deutsch, B. Keller, V. Chickermane, S.K. Goel and E.J. Marinissen, “DfT insertion and interconnect test generation for 3D stacks with JEDEC wide-IO DRAM”, IEEE North-Atlantic Test Workshop (NATW), MA, 2012
 

S. Deutsch, V. Chickermane, B. Keller, S. Mukherjee, M. Konijnenburg, E.J. Marinissen, and S.K. Goel, “Automation of 3D-DFT”, IEEE International Workshop on Testing Three-Dimensional Stacked ICs, CA, 2011

 

C.C. Chi, E.J. Marinissen, S.K. Goel, and C.W. Wu, “DFT architecture for multi-tower 3D SICs”, 3D Integration-Application, Technology, Architecture, Design Automation and Test workshop at Design Automation and Test in Europe (DATE), France, 2011

 

P. Ren, G. Gaydadijev, A.M. Amory, M. Lubaszewski, E.J. Marinissen, K. Goossens, S.K. Goel, and F. Moraes, “Test wrapper design that allows a core to be rested via a NOC or other functional interconnects”, Diagnostic Services in Network-on-Chip Workshop at Design Automation and Test in Europe (DATE), France, 2007

 

S.K. Goel and E.J. Marinissen, "Test infrastructure design for high-throughput multi-site testing of system chips", IEEE Infrastructure IP Workshop (IIP), NC, USA,  2004

 

Z. Urfianto, S.K. Goel, and B. Vermeulen, "Automatic generation of breakpoint hardware for silicon debug", IEEE Infrastructure IP Workshop (IIP), NC, USA, 2003

 

V. Iyenger, S.K. Goel, E.J. Marinissen, and K. Chakrabarty, "On SOC test resource optimization for multi-site testing using ATE with memory depth constraints", IEEE North Atlantic Test Workshop (NATW), MA, 2002

 

V. Iyenger, S.K. Goel, E.J. Marinissen, and K. Chakrabarty, "On SOC test resource optimization for multisite testing using ATE with memory depth constraints", IEEE European Test Workshop (ETW), Greece,  2002

 

S.K. Goel and E.J. Marinissen, "TAM architectures and their implications on test application time", IEEE International Workshop on Testing of Core-Based System Chips (TECS), CA,  2001

 

 

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